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language/Verilog

[vcs] $dumpvars option

by 파란하늘코더 2021. 3. 12.
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VCS를 이용하여 FSDB를 dumping 받을 때 사용하는 system task인 $dumpvars의 option을

 

항상 매뉴얼보고 확인하기 힘들어 여기에 정리합니다.

 

option description
"+IO_Only" Only IO port signals will be dumped.
"+Reg_Only"Only reg type signals will be dumped.
"+mda"Dump all memory and MDA signals in all scopes specified in
$fsdbDumpvars or the entire design if no scope is specified.
This option is covered by the "+all" option and is effective for SystemVerilog's MDAs only.For VCS users, the VCS option
"+memcbk" may be needed while compiling the design.

*NOTE*: This option does not apply to VHDL arrays because they are dumped by default without this option.

Example: $fsdbDumpvars("+mda");
"+mda+packedOnly"Dump the packed signals in the design. Refer to the Supported
MDA Format Table for a summary of which packed or unpacked
one-dimensional/two-dimensional signals are dumped with or without
the +mda+packedOnly and +mda options.
This option is covered by the "+mda" option.

Example: $fsdbDumpvars("+mda+packedOnly");
"+struct"Dump struct, MDA struct (i.e. st2[0:1]), MDA in struct (i.e. | | | st3.r[1:0][2:0])
and packed MDA in all scopes specified in if no scope is specified.
$fsdbDumpvars or the entire design Unpacked array/MDA will not be dumped.
"+struct" is not needed if "+all" is specified.

Example: $fsdbDumpvars("+struct");
"+skip_cell_instance=mode"Enable/Disable dumping of cell instance where mode means:

0: disable functionality.
1: Skip all cell info.
2: Dump all ports of cell instance.
Others: Show error message and ignore it.

Example: $fsdbDumpvars("+skip_cell_instance");
"+strength"Enable strength dumping.

Example: $fsdbDumpvars("+strength");
"+all" Dump all signals including the memory, MDA, packed array, structure,
union and packed structure signals in all scopes specified
in $fsdbDumpvars or the entire design if no scope is specified.
For VCS users, the VCS option "+memcbk" may be needed when compiling the design.
"+parameter" Dump parameters.

Example: $fsdbDumpvars("+parameter");
"+trace_process"Dump VHDL processes.

Example: $fsdbDumpvars("+trace_process");
"+no_functions"Disable dumping of functions in the design.

Example: $fsdbDumpvars("+no_functions");
"+fsdbfile+filename"Specify the FSDB file name.
If not specified, the default FSDB file name is "novas.fsdb".

참조 : github.com/hjking/mydotfiles/blob/master/vim/vim_wiki/eda/verdi/Linking_And_Dumping.wiki

 

hjking/mydotfiles

my rc files. Contribute to hjking/mydotfiles development by creating an account on GitHub.

github.com

 

 

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